/*
  ******************************************************************************
  * @file    apt32f172_tc1_gtc.c
  * @author  APT AE Team
  * @version V1.12
  * @date    2019/03/08
  ******************************************************************************
  *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES 
  *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
  *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, 
  *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF 
  *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION 
  *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES 
  *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/ 
#include "apt32f172_tc1_gtc.h"
/* defines -------------------------------------------------------------------*/

/* externs--------------------------------------------------------------------*/


/*************************************************************/
//GTC RESET VALUE
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void GTC_RESET_VALUE(void)									//reset value
{
	GTC->IDR 	= GTC_IDR_RST;											/**< IDR reset value         */    
	GTC->CSSR 	= GTC_CSSR_RST;	     								   	/**< CSSR reset value        */
	GTC->CEDR 	= GTC_CEDR_RST;  	 									/**< CEDR reset value        */
	GTC->SRR 	= GTC_SRR_RST;             								/**< SRR reset value         */
	GTC->CSR 	= GTC_CSR_RST;             	 							/**< CSR reset value         */
	GTC->CCR 	= GTC_CCR_RST;              							/**< CCR reset value         */
	GTC->SR 	= GTC_SR_RST;           								/**< SR reset value          */
	GTC->IMSCR 	= GTC_IMSCR_RST;        								/**< IMSCR reset value       */
	GTC->RISR	= GTC_RISR_RST;          								/**< RISR reset value        */
	GTC->MISR 	= GTC_MISR_RST;         								/**< MIS reset value        */
	GTC->ICR 	= GTC_ICR_RST;          								/**< ICR reset value         */
	GTC->CDR 	= GTC_CDR_RST;        									/**< SR reset value          */
	GTC->CSMR 	= GTC_CSMR_RST;           								/**< SR reset value          */
	GTC->PRDR 	= GTC_PRDR_RST;           								/**< DR reset value          */
	GTC->PULR	= GTC_PULR_RST;          								/**< SR reset value          */
	GTC->CUCR 	= GTC_CUCR_RST;         								/**< SR reset value          */
	GTC->CDCR 	= GTC_CDCR_RST;            								/**< SR reset value          */
	GTC->CVR	= GTC_CVR_RST;											/**< CVR reset value         */
}
/*************************************************************/
//gtc Configure
//EntryParameter:GTC_FIN_X,GTC_DIVN,GTC_DINM,Counter_Size_X,loadCounter_PRDR,loadCounter_PULR
//GTC_FIN_X:GTC_FIN_PCK,GTC_FIN_TCLK0,GTC_FIN_TCLK2,GTC_FIN_CountA,GTC_FIN_IMOSC
//GTC_DIVN:VALUE=0~15
//GTC_DINM:0~255
//Counter_Size_X:Counter_Size_8BIT,Counter_Size_10BIT,Counter_Size_16BIT,Counter_Size_32BIT
//loadCounter_PRDR:Timer/Counter Period Data Register
//loadCounter_PULR:loadCounter_PULR<loadCounter_PRDR  (attention)
//ReturnValue:NONE
/*************************************************************/  
  //TCCLK=FIN/2^DIVN/(DINM+1)  GTC_FIN_TypeDef;
  //It is forbidden to set DIVM to zero when DIVN is not zero
void GTC_Configure(GTC_FIN_TypeDef  GTC_FIN_X, int  GTC_DIVN , int  GTC_DINM , Counter_Size_TypeDef  Counter_Size_X  , U32_T loadCounter_PRDR , U32_T loadCounter_PULR)
{
	GTC->CSSR = GTC_FIN_X;													//selected GTC clk
	GTC->CEDR = GTC_CLKEN|GTC_DBGEN;										//ENABLE GTC CLK
	GTC->CDR = GTC_DIVN|(GTC_DINM<<4);										//DIVN and DINM set
	GTC->CSMR = Counter_Size_X;												//selected GTC conter size
	GTC->PRDR = loadCounter_PRDR;											//Period of GTC date register
	GTC->PULR = loadCounter_PULR;											//Pulse of GTC date register
}

/*************************************************************/
//gtc Timer/Counter Control Set Register
//EntryParameter:GTC_ControlSet_x,NewState
//GTC_ControlSet_x:Reference library
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/  
void GTC_ControlSet_Configure (GTC_ControlSet_TypeDef GTC_ControlSet_x , FunctionalStatus NewState)
{
	if (NewState != DISABLE)
	{
		GTC->CSR |= GTC_ControlSet_x;
		if(GTC_ControlSet_x)
		{
			while(!(GTC->SR&GTC_ControlSet_x));
		}
	}
	else
	{
		GTC->CCR |= GTC_ControlSet_x;
		while(GTC->SR&GTC_ControlSet_x);
	}
}

/*************************************************************/
//gtc inturrpt Configure
//EntryParameter:GTC_IMSCR_X,NewState
//GTC_IMSCR_X:GTC_STARTI,GTC_STOPI,GTC_PSTARTI,GTC_PENDI,GTC_MATI,GTC_OVFI,GTC_CAPTI
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/ 
void GTC_ConfigInterrupt_CMD(GTC_IMSCR_TypeDef GTC_IMSCR_X , FunctionalStatus NewState)
{
	if (NewState != DISABLE)
	{
		GTC->IMSCR  |= GTC_IMSCR_X;						//SET
	}
	else
	{
		GTC->IMSCR  &= ~GTC_IMSCR_X;					//CLR
	}
}

/*************************************************************/
//gtc software reset
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void GTC_SoftwareReset(void)
{
	GTC->SRR = GTC_SWRST;							// Software reset
}
  
/*************************************************************/
//gtc start stop
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void GTC_start_stop(void)
{
	GTC_ControlSet_Configure (GTC_ControlSet_start_stop , ENABLE); 
}
/*************************************************************/
//gtc start
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void GTC_Start(void)
{
	GTC_ControlSet_Configure (GTC_ControlSet_start_stop , ENABLE); 
}
/*************************************************************/
//gtc stop
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void GTC_Stop(void)
{
	GTC_ControlSet_Configure (GTC_ControlSet_start_stop , DISABLE); 
}
/*************************************************************/
// gtc counter read
//EntryParameter:
//ReturnValue:Counter value
/*************************************************************/ 
/*U32_T GTC_Counter_Value(void)
{
	return (GTC->CVR);
}*/
/*************************************************************/
//gtc counter period DATA read 
//EntryParameter:loadCounter_PRDR,loadCounter_PULR
//ReturnValue:Conter prdr register value
/*************************************************************/  
void GTC_Set_Period(U32_T loadCounter_PRDR , U32_T loadCounter_PULR)
{
	GTC->CSR = (GTC->CSR & 0xFFFFFFFD) | 0x02;
	while(!((GTC->SR & 0x02)==0X02));
	GTC->PRDR = loadCounter_PRDR;											//Period of GTC date register
	GTC->PULR = loadCounter_PULR;											//Pulse of GTC date register
}
/*************************************************************/
//gtc counter period DATA read 
//EntryParameter:
//ReturnValue:Conter prdr register value
/*************************************************************/ 
/*U32_T GTC_Counter_PRDR_Value(void)
{
	return (GTC->PRDR);
}*/

/*************************************************************/
//gtc CaptureUp Count Value read 
//EntryParameter:
//ReturnValue:CaptureUp Count Value
/*************************************************************/ 
/*U32_T GTC_CaptureUp_Count_Value(void)
{
	return (GTC->CUCR);
}*/

/*************************************************************/
//gtc CaptureDown Count Value read 
//EntryParameter:
//ReturnValue:CaptureDown Count Value
/*************************************************************/ 
/*U32_T GTC_CaptureDown_Count_Value(void)
{
	return (GTC->CDCR);
}*/
/*************************************************************/
//GTC Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GTC_Int_Enable(void)
{
    INTC_ISER_WRITE(TC1_INT);    
}

/*************************************************************/
//GTC Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GTC_Int_Disable(void)
{
    INTC_ICER_WRITE(TC1_INT);    
}
/*************************************************************/
//GTC Interrupt wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GTC_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(TC1_INT);    
}

/*************************************************************/
//GTC Interrupt wake up disalbe
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GTC_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(TC1_INT);    
}
/*************************************************************/
//GTC IO Init
//EntryParameter:GTC_IO_MODE_X,GTC_IO_G
//GTC_IO_MODE_X:GTC_IO_TXOUT,GTC_IO_TCLK,GTC_IO_TCAPX
//GTC_IO_G;GTC_IO_TXOUT(0->PB0.00 ;1->PA0.06;2->PC0.02;3->PA0.15),GTC_IO_TCLK(0->PA0.0),GTC_IO_TCAPX(0->PA1.0;1->PA1.1)
//ReturnValue:NONE
/*************************************************************/
void GTC_IO_Init(GTC_IO_MODE_TypeDef  GTC_IO_MODE_X , U8_T GTC_IO_G )
{
	if(GTC_IO_MODE_X==GTC_IO_TXOUT)
	{
		if(GTC_IO_G==0)
		{
			GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFFF0)|0x00000006;										//T1OUT(PB0.00->AF3)
		}
		else if(GTC_IO_G==1)
		{
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XF0FFFFFF)|0x05000000;										//T1OUT(PA0.06->AF2)
		}
		else if(GTC_IO_G==2)
		{
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFF0FF)|0x00000500;										//T1OUT(PC0.02->AF2)
		}
		else if(GTC_IO_G==3)
		{
			GPIOA0->CONHR=(GPIOA0->CONHR & 0X0FFFFFFF)|0x40000000;										//T1OUT(PA0.15->AF1)
		}
	}
	else if(GTC_IO_MODE_X==GTC_IO_TCLK)
	{
		if(GTC_IO_G==0)
		{
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x00000005;										//TCLK(PA0.0->AF2)
		}
	}
	else if(GTC_IO_MODE_X==GTC_IO_TCAPX)
	{
		if(GTC_IO_G==0)
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFFF0)|0x00000006;										//TCAP1(PA1.0->AF3)
		}	
		else if(GTC_IO_G==1)
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFF0F)|0x00000040;										//TCAP1(PA1.1->AF1)
		}
	}
}

/******************* (C) COPYRIGHT 2018 APT Chip *****END OF FILE****/